View AD641ANZ_9038737.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad641 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 w orld wide web site: http://www.analog.com f a x : 781/326-8703 ? analog devices, inc., 1999-2016 250 mhz demodulating logarithmic amplifier features logarithmic amplifier performance usable to 250 mhz 44 db dynamic range 6 2.0 db log conformance 37.5 mv/db voltage output stable slope and intercepts 2.0 nv/ ? hz input noise voltage 50 m v input offset voltage low power 6 5 v supply operation 9 ma (+v s ), 35 ma (Cv s ) quiescent current onboard resistors onboard 10 3 attenuator dual polarity current outputs direct coupled differential signal path applications if/rf signal processing received signal strength indicator (rssi) high speed signal compression high speed spectrum analyzer ecm/radar pin configurations 20-lead plastic dip (n) 20-lead cerdip (q) top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad641 atn com ckt com Cinput atn lo atn com atn in bl1 Cv s itc Coutput bl2 atn out +input rg1 rg0 rg2 log out log com +v s +output 20-lead plcc (p) 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 top view (not to scale) pin 1 identifier atn com ckt com ad641 atn com atn lo Cinput +input atn out bl2 sig Cout sig +out +v s log com atn in bl1 Cv s itc rg1 rg0 rg2 log out product description the ad641 is a 250 mhz, demodulating logarithmic amplifier with an accuracy of 2.0 db and 44 db dynamic range. the ad641 uses a successive detection architecture to provide an output current that is logarithmically proportional to its input voltage. the output current can be converted to a voltage using one of several on-chip resistors to select the slope. a single ad641 provides up to 44 db of dynamic range at speeds up to 250 mhz, and two cascaded ad641s together can provide 58 db of dynamic range at speeds up to 250 mhz. the ad641 is fully stable and well characterized over either the industrial or military temperature ranges. the ad641 is not a logarithmic building block, but rather a complete logarithmic solution for compressing and measuring wide dynamic range signals. the ad641 is comprised of five stages and each stage has a full wave rectifier, whose current depends on the absolute value of its input voltage. the output of these stages are summed together to provide the demodulated output current scaled at 1 ma per decade (50 m a/db). without utilizing the 10 input attenuator, log conformance of 2.0 db is maintained over the input range C44 dbm to 0 dbm. the attenuator offers the most flexibility without significantly impacting performance. the 250 mhz bandwidth and temperature stability make this product ideal for high speed signal power measurement in rf/ if systems. ecm/radar and communication applications are routinely in the 100 mhzC180 mhz range for power measure- ment. the bandwidth and accuracy, as well as dynamic range, make this part ideal for high speed, wide dynamic range signals. the ad641 is offered in industrial (C40 c to +85 c) and mili- tary (C55 c to +125 c) package temperature ranges. industrial versions are available in plastic dip and plcc; mil versions are packaged in cerdip.
rev. d C2C ad641Cspecifications electrical characteristics ad641a ad641s parameter conditions min typ max min typ max units transfer function 1 (i out = i y log |v in /v x |for v in = 0.75 mv to 200 mv dc) log amplifier performance 3 db bandwidth 250 250 mhz voltage compliance range C0.3 +v s C 1 C0.3 +v s C 1 v slope current, i y 0.98 1.00 1.02 0.98 1.00 1.02 ma accuracy vs. temperature 0.002 0.002 %/ c over temperature t min to t max 0.9 6 1.02 ma intercept dbm 250 mhz C 4 1 . 06 C40. 51 C39.96 C4 1 . 06 C40. 51 C39.96 dbm over temperature t min to t max , 250 mhz C 4 1 . 34 C39.47 dbm zero signal output current 2 C0.2 C0.2 ma itc disabled pin 8 to com C0.27 C0.27 ma maximum output current 2.3 2.3 ma dynamic range single configuration 44 44 db over temperature t min to t max 40 38 db dual configuration 58 58 db over temperature t min to t max 52 52 db log conformance f = 250 mhz single configuration C44 dbm to 0 dbm 0.5 2.0 0.5 2.0 db over temperature C42 dbm to C4 dbm; t min to t max 1.0 2.5 db C42 dbm to C2 dbm, t min to t max 1.0 2.5 dual configuration s: C60 dbm to C2 dbm; 0.5 2.0 0.5 2.0 db over temperature a: C56 dbm to C4 dbm, t min to t max 1.0 2.5 1.0 2.5 db limiter characteristics flatness C44 dbm to 0 dbm @ 10.7 mhz 1.6 1.6 db phase variation C44 dbm to 0 dbm @ 10.7 mhz 2.0 2.0 degrees input characteristics input resistance differential 500 500 k w input offset voltage differential 50 200 50 200 m v vs. temperature 0.8 0.8 m v/ c over temperature t min to t max 300 m v vs. supply 22 m v/v input bias current 7 25 7 25 m a input bias offset 11 m a common mode input range C2 +0.3 C2 +0.3 v signal input (pins 1, 20) input capacitance either pin to com 2 2 pf noise spectral density 1 khz to 10 mhz 2 2 nv/ ? hz tangential sensitivity bw = 100 mhz C72 C72 dbm input attenuator (pins 2, 3, 4, 5 & 19) attenuation 3 pins 5 to pin 19 20 20 db input resistance pins 5 to 3/4 300 300 w application resistors (pins 15, 16, 17) 0.995 1.000 1.005 0.995 1.000 1.005 k w output characteristics (pins 10, 11) peak differential output 4 180 180 mv output resistance either pin to com 75 75 w quiescent output voltage either pin to com C90 C90 mv power supply voltage supply range 4.5 7.5 4.5 7.5 v quiescent current +v s (pin 12) t min to t max 915 9 15 ma Cv s (pin 7) t min to t max 35 60 35 60 ma notes 1 logarithms to base 10 are used throughout. the response is independent of the sign of v in . 2 the zero-signal current is a function of temperature unless internal temperature compensation (itc) pin is grounded. 3 attenuation ratio trimmed to calibrate intercept to 10 mv when in use. it has a temperature coefficient of +0.3%/ c. 4 the fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature. specifications subject to change wi thout notice. (v s = 6 5 v; t a = +25 8 c, unless otherwise noted)
rev. d ad641 C3C thermal characteristics u jc u ja ( 8 c/w) ( 8 c/w) 20-lead plastic dip package (n) 24 61 20-lead cerdip package (q) 25 85 20-lead plastic leadless chip carrier (p) 28 75 absolute maximum ratings* supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 v input voltage (pin 1 or pin 20 to com) . . . C3 v to +300 mv attenuator input voltage (pin 5 to pin 3/4) . . . . . . . . . . . 4 v storage temperature range, q . . . . . . . . . . C65 c to +150 c storage temperature range, n, p . . . . . . . . C65 c to +125 c ambient temperature range, rated performance industrial, ad641a . . . . . . . . . . . . . . . . . . C40 c to +85 c military, ad641s . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad641 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device revision history 6 / 20 16--rev. c to rev. d changes to log amplifier performance, slope current, i y over temperature parameter ad61s only...........................................................2 changes to log amplifier performance, intercept dbm parameter...........................................................2 changes to log amplifier performance, intercept dbm, over temperature parameter........................2 moved ordering guide...........................................16 updated outline dimensions ................................16 added revision history section .................. ............ 3
rev. d ad641 C4C Ctypical dc performance characteristics 1.015 1.010 1.005 1 0.995 0.990 0.985 0.980 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c slope current C ma figure 1. slope current, i y , vs. temperature 4.5 5.0 5.5 6.0 6.5 7.0 7.5 power supply voltages C 6 volts intercept voltage C mv 1.015 1.010 1.005 1.000 0.995 0.990 0.985 figure 4. intercept voltage, v x , vs. supply voltages input voltage C mv ( either sign ) output current C ma 2 1.0 0.1 1.0 1000.0 10.0 100.0 1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.8 0.6 0.4 0.2 0 C0.2 C0.4 error C db 0 figure 7. dc logarithmic transfer function and error curve for single ad641 1.20 1.15 1.10 1.05 1.00 0.95 0.90 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c intercept C mv 0.85 figure 2. intercept voltage, v x , vs. temperature 14 13 12 11 10 9 8 7 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c intercept C mv figure 5. intercept voltage (using attenuator) vs. temperature 2.5 2.0 1.5 1.0 0.5 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c 0 absolute error C db figure 8. absolute error vs. tempera- ture, v in = 1 mv to 100 mv 4.5 5.0 5.5 6.0 6.5 7.0 7.5 power supply voltages C 6 volts slope current C mv 1.006 1.004 1.002 1.000 0.998 0.996 0.994 figure 3. slope current, i y , vs. supply voltages C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c deviation of input offset voltage C mv 0 C0.1 +0.4 +0.3 +0.2 +0.1 C0.2 C0.3 input offset voltage deviation will be within shaded area. figure 6. input offset voltage devia- tion vs. temperature 2.5 2.0 1.5 1.0 0.5 C60 C40 C20 0 20 40 60 80 100 120 140 temperature C 8c 0 absolute error C db figure 9. absolute error vs. tempera- ture, using attenuator. v in = 10 mv to 1 v, pin 8 grounded to disable itc bias
rev. d ad641 C5C typical ac performance characteristicsC input level C dbm C2.25 C2.00 0.25 2 C48 C44 C40 C4 C1.25 C0.50 C0.25 0.00 C1.75 C1.50 C0.75 C1.00 output current C ma C52 C36 C32 C28 C24 C20 C16 C12 C8 0 50mhz 150mhz 190mhz 210mhz 250mhz figure 10. ac response at 50 mhz, 150 mhz, 190 mhz, 210 mhz at 250 mhz, vs. dbm input (sinusoidal input) input frequency C mhz intercept level C dbm 87.5 70.0 50 250 100 150 170 190 210 230 85.0 80.0 77.5 75.0 72.5 82.5 figure 11. intercept level (dbm) vs. frequency (cascaded ad641ssinusoidal input) figure 12. baseband pulse response of single ad641, inputs of 1 mv, 10 mv and 100 mv error in C db input level C dbm C2.00 C1.75 0.50 2 C48 C44 C40 C4 C1.00 C0.25 C0.00 0.25 C1.50 C1.25 C0.50 C0.75 output C ma C52 C36 C32 C28 C24 C20 C16 C12 C8 0 +25 8c +125 8c C55 8c +258c +125 8c C558c output +258c +125 8c C55 8c +125 8c error +258c C558c 5 4 3 2 1 0 C1 C2 C3 C4 C5 figure 13. logarithmic response and linearity at 200 mhz, t a for t a = C55 c, +25 c, +125 c input frequency C mhz 1.0 0.95 0.75 50 250 150 190 210 0.90 0.85 0.80 slope current C ma figure 14. slope current, i y , vs. input frequency 10 0% 5s 5s 20mv 20mv 100 90 figure 15. baseband pulse response of cascaded ad641s at inputs of 0.2 mv, 2 mv, 20 mv and 200 mv
rev. d ad641 C6C atn lo atn com sig +in sig Cin atn com com 27v 30v 270v atn in 1kv 1kv rg1 rg0 rg2 Cv s bl1 +v s log out log com sig +out sig Cout bl2 itc 20 gain bias regulator amplifier/limiter full-wave detector 10db amplifier/limiter full-wave detector 10db amplifier/limiter full-wave detector 10db amplifier/limiter full-wave detector 10db amplifier/limiter full-wave detector 10db atn out 1 2 3 6 4 5 19 18 7 13 9 8 11 10 12 slope bias regulator intercept positioning bias 14 15 16 17 figure 17. block diagram of the complete ad641 circuit description the ad641 uses five cascaded limiting amplifiers to approxi- mate a logarithmic response to an input signal of wide dynamic range and wide bandwidth. this type of logarithmic amplifier has traditionally been assembled from several small scale ics and numerous external components. the performance of these semidiscrete circuits is often unsatisfactory. in particular, the logarithmic slope and intercept (see fundamentals of logarithmic conversion) are usually not very stable in the presence of supply and temperature variations even after laborious and expensive individual calibration. the ad641 em- ploys high precision analog circuit techniques to ensure stability of scaling over wide variations in supply voltage and tempera- ture. laser trimming, using ac stimuli and operating conditions similar to those encountered in practice, provides fully cali- brated logarithmic conversion. each of the amplifier/limiter stages in the ad641 has a small signal voltage gain of 10 db ( 3.162) and a C3 db bandwidth of 350 mhz. fully differential direct coupling is used throughout. this eliminates the many interstage coupling capacitors usually required in ac applications, and simplifies low frequency signal processing, for example, in audio and sonar systems. the ad641 is intended for use in demodulating applications. each stage incorporates a detector (a full-wave transconductance rectifier) whose output current depends on the absolute value of its input voltage. figure 16 is a simplified schematic of one stage of the ad641. all transistors in the basic cell operate at near zero collector to base voltage and low bias currents, resulting in low levels of thermally induced distortion. these arise when power shifts from one set of transistors to another during large input signals. rapid recovery is essential when a small signal immediately follows a large one. this low power operation also contributes significantly to the excellent long term calibration stability of the ad641. the complete ad641, shown in figure 17, includes two bias regulators. one determines the small signal gain of the ampli- fier stages; the other determines the logarithmic slope. these bias regulators maintain a high degree of stability in the re- sulting function by compensating for potentially large uncer- tainties in transistor parameters, temperature and supply voltages. a third biasing block is used to accurately control the logarithmic intercept. common sig in r1 85v r2 85v r3 75v r4 75v sig out log out log com q1 q2 q3 q4 q5 q6 q7 q8 q10 q9 Cv s 1.09ma ptat 1.09ma ptat 565ma 565ma 2.18ma ptat figure 16. simplified schematic of a single ad641 stage by summing the signals at the output of the detectors, a good approximation to a logarithmic transfer function can be achieved. the lower the stage gain, the more accurate the approximation, but more stages are then needed to cover a given dynamic range. the choice of 10 db results in a theoretical periodic deviation or ripple in the transfer function of 0.15 db from the ideal re- sponse when the input is either a dc voltage or a square wave. the slope of the transfer function is unaffected by the input waveform; however, the intercept and ripple are waveform de- pendent (see effect of waveform on intercept). the input will usually be an amplitude modulated sinusoidal carrier. in these circumstances the output is a fluctuating cur- rent at twice the carrier frequency (because of the full wave detection) whose average value is extracted by an external low pass filter, which recovers a logarithmic measure of the base- band signal. circuit operation with reference to figure 16, the transconductance pair q7, q8 and load resistors r3 and r4 form a limiting amplifier having a small signal gain of 10 db, set by the tail current of nominally 2.18 ma at 27 c. this current is basically proportional to abso- lute temperature (ptat) but includes additional current to compensate for finite beta and junction resistance. the limiting output voltage is 180 mv at +27 c and is ptat. emitter followers q1 and q2 raise the input resistance of the stage, provide level shifting to introduce collector bias for the gain stage and detectors, reduce offset drift by forming a thermally balanced quad with q7 and q8 and generate the detector bias- ing across resistors r1 and r2.
rev. d ad641 C7C transistors q3 through q6 form the full wave detector, whose output is buffered by the cascodes q9 and q10. for zero input q3 and q5 conduct only a small amount (a total of about 32 m a) of the 565 m a tail currents supplied to pairs q3Cq4 and q5Cq6. this pedestal current flows in output cascode q9 to the log out node (pin 14). when driven to the peak output of the preceding stage, q3 or q5 (depending on signal polarity) con- ducts most of the tail current, and the output rises to 532 m a. the log out current has thus changed by 500 m a as the input has changed from zero to its maximum value. since the detectors are spaced at 10 db intervals, the output increases by 50 m a/db, or 1 ma per decade. this scaling parameter is trimmed to absolute accuracy using a 2 khz square wave. at frequencies near the system bandwidth, the slope is reduced due to the reduced output of the limiter stages, but it is still relatively in- sensitive to temperature variations so that a simple external slope adjustment can restore scaling accuracy. the intercept position bias generator (figure 17) removes the pedestal current from the summed detector outputs. it is ad- justed during manufacture such that the output (flowing into pin 14) is 1 ma when a 2 khz square-wave input of exactly 10 mv is applied to the ad641. this places the dc intercept at precisely 1 mv. the log com output (pin 13) is the comple- ment of log out. it also has a 1 mv intercept, but with an inverted slope of C1 ma/decade. because its pedestal is very large (equivalent to about 100 db), its intercept voltage is not guaranteed. the intercept positioning currents include a special internal temperature compensation (itc) term which can be disabled by connecting pin 8 to ground. the logarithmic function of the ad641 is absolutely calibrated to within 0.3 db (or 15 m a) for 2 khz square-wave inputs of 1 mv to 100 mv, and to within 1 db between 750 m v and 200 mv. figure 18 is a typical plot of the dc transfer function, 2.5 C0.5 1000.0 0.5 0 1.0 0.1 1.0 1.5 2.0 100.0 10.0 input voltage C mv output current C ma 2 1 0 C1 C2 3 absolute error C db C558c +1258c +258c +1258c C558c +258c figure 18. logarithmic output and absolute error vs. dc or square wave input at t a = C55 c, +25 c, and +125 c, input direct to pins 1 and 20 2.5 C0.5 10000 0.5 0 10 0.1 1.0 1.5 2.0 1000 100 input voltage C mv output current C ma 1 0 C1 C2 absolute error C db +258c C558c +858c +1258c figure 19. logarithmic output and absolute error vs. dc or square wave input at t a = C55 c, +25 c, +85 c and +125 c. input via on-chip attenuator showing the outputs at temperatures of C55 c, +25 c and +125 c. while the slope and intercept are seen to be little af- fected by temperature, there is a lateral shift in the end points of the linear region of the transfer function, which reduces the effective dynamic range. the on chip attenuator can be used to handle input levels 20 db higher, that is, from 7.5 mv to 2 v for dc or square wave inputs. it is specially designed to have a positive temperature coefficient and is trimmed to position the intercept at 10 mv dc (or C24 dbm for a sinusoidal input) over the full temperature range. when using the attenuator the internal bias compensa- tion should be disabled by grounding pin 8. figure 19 shows the output at C55 c, +25 c, +85 c and +125 c for a single , ad641 with the attenuator in use; the curves overlap almost perfectly, and the lateral shift in the transfer function does not occur. therefore, the full dynamic range is available at all temperatures. the output of the final limiter is available in differential form at pins 10 and 11. the output impedance is 75 w to ground from either pin. for most input levels, this output will appear to have roughly a square waveform. the signal path may be extended using these outputs (see operation of cascaded ad641s). the logarithmic outputs from two or more ad641s can be directly summed with full accuracy. a pair of 1 k w applications resistors, rg1 and rg2 (figure 17) are accessed via pins 15, 16 and 17. these can be used to con- vert an output current to a voltage, with a slope of 1 v/decade (using one resistor), 2 v/decade (both resistors in series) or 0.5 v/decade (both in parallel). using all the resistors from two ad641s (for example, in a cascaded configuration) ten slope options from 0.25 v to 4 v/decade are available.
rev. d ad641 C8C fundamentals of logarithmic conversion the conversion of a signal to its equivalent logarithmic value involves a nonlinear operation, the consequences of which can be very confusing if not fully understood. it is important to realize from the outset that many of the familiar concepts of linear circuits are of little relevance in this context. for example, the incremental gain of an ideal logarithmic converter approaches infinity as the input approaches zero. further, an offset at the output of a linear amplifier is simply equivalent to an offset at the input, while in a logarithmic converter it is equivalent to a change of amplitude at the inputa very different relationship. we assume a dc signal in the following discussion to simplify the concepts; ac behavior and the effect of input waveform on cali- bration are discussed later. a logarithmic converter having a voltage input v in and output v out must satisfy a transfer func- tion of the form v out = v y log (v in /v x ) equation (1) where v y and v x are fixed voltages which determine the scaling of the converter. the input is divided by a voltage because the argument of a logarithm has to be a simple ratio. the logarithm must be multiplied by a voltage to develop a voltage output. these operations are not, of course, carried out by explicit com- putational elements, but are inherent in the behavior of the converter. for stable operation, v x and v y must be based on sound design criteria and rendered stable over wide temperature and supply voltage extremes. this aspect of rf logarithmic amplifier design has traditionally received little attention. when v in = v x , the logarithm is zero. v x is, therefore, called the intercept voltage, because a graph of v out versus log (v in )ideally a straight linecrosses the horizontal axis at this point (see figure 20). for the ad641, v x is calibrated to ex- actly 1 mv. the slope of the line is directly proportional to v y . base 10 logarithms are used in this context to simplify the rela- tionship to decibel values. for v in = 10 v x , the logarithm has a value of 1, so the output voltage is v y. at v in = 100 v x , the output is 2 v y , and so on. v y can therefore be viewed either as the slope voltage or as the volts per decade factor. the ad641 conforms to equation (1) except that its two out- puts are in the form of currents, rather than voltages: i out = i y log (v in /v x ) equation (2) actual 0 input on log scale y y 2v y ideal v y log (v in /v x ) v in = v x v in = 100v x v in = 10v x actual slope = v y ideal + C figure 20. basic dc transfer function of the ad641 i y , the slope current, is 1 ma. the current output can readily be converted to a voltage with a slope of 1 v/decade, for ex- ample, using one of the 1 k w resistors provided for this purpose, in conjunction with an op amp, as shown in figure 21. 9 12 8 13 7 14 6 15 10 11 log out log com sig +out +v s Cv s itc bl2 sig Cout ad641 c1 330pf 1ma per decade ad846 r1 48.7v r2 output voltage 1v per decade for r2 = 1kv 100mv per db for r2 = 2kv figure 21. using an external op amp to convert the ad641 output current to a buffered voltage output intercept stabilization internally, the intercept voltage is a fraction of the thermal volt- age kt/q, that is, v x = v xo t/t o , where v xo is the value of v x at a reference temperature t o . so the uncorrected transfer function has the form: i out = i y log (v in t o /v xo t) equation (3) now, if the amplitude of the signal input v in could somehow be rendered ptat, the intercept would be stable with tempera- ture, since the temperature dependence in both the numerator and denominator of the logarithmic argument would cancel. this is what is actually achieved by interposing the on-chip attenuator, which has the necessary temperature dependence to cause the input to the first stage to vary in proportion to abso- lute temperature. the end limits of the dynamic range are now totally independent of temperature. consequently, this is the pre- ferred method of intercept stabilization for applications where the input signal is sufficiently large. when the attenuator is not used, the ptat variation in v x will result in the intercept being temperature dependent. near 300k (+27 c) it will vary by 20 log (301/300) db/ c, about 0.03 db/ c. unless corrected, the whole output function would drift up or down by this amount with changes in temperature. in the ad641 a temperature compensating current i y log(t/t o ) is added to the output. this effectively maintains a constant inter- cept v xo . this correction is active in the default state (pin 8 open circuited). when using the attenuator, pin 8 should be grounded, which disables the compensation current. the drift term needs to be compensated only once; when the outputs of two ad641s are summed, pin 8 should be grounded on at least one of the two devices (both if the attenuator is used). conversion range practical logarithmic converters have an upper and lower limit on the input, beyond which errors increase rapidly. the upper limit occurs when the first stage in the chain is driven into limit- ing. above this, no further increase in the output can occur and the transfer function flattens off. the lower limit arises because a finite number of stages provide finite gain, and therefore at low signal levels the system becomes a simple linear amplifier.
rev. d ad641 C9C note that this lower limit is not determined by the intercept voltage, v x ; it can occur either above or below v x , depending on the design. when using two ad641s in cascade, input offset voltage and wideband noise are the major limitations to low level accuracy. offset can be eliminated in various ways. noise can only be reduced by lowering the system bandwidth, using a filter between the two devices. effect of waveform on intercept the absolute value response of the ad641 allows inputs of either polarity to be accepted. thus, the logarithmic output in response to an amplitude-symmetric square wave is a steady value. for a sinusoidal input the fluctuating output current will usually be low-pass filtered to extract the baseband signal. the unfiltered output is at twice the carrier frequency, simplifying the design of this filter when the video bandwidth must be maxi- mized. the averaged output depends on waveform in a roughly analogous way to waveform dependence of rms value. the effect is to change the apparent intercept voltage. the intercept volt- age appears to be doubled for a sinusoidal input, that is, the averaged output in response to a sine wave of amplitude (not rms value) of 20 mv would be the same as for a dc or square wave input of 10 mv. other waveforms will result in different inter- cept factors. an amplitude-symmetric-rectangular waveform has the same intercept as a dc input, while the average of a base- band unipolar pulse can be determined by multiplying the response to a dc input of the same amplitude by the duty cycle. it is important to understand that in responding to pulsed rf signals it is the waveform of the carrier (usually sinusoidal) not the modulation envelope, that determines the effective intercept voltage. table i shows the effective intercept and resulting deci- bel offset for commonly occurring waveforms. the input wave- form does not affect the slope of the transfer function. figure 22 shows the absolute deviation from the ideal response of cascaded ad641s for three common waveforms at input levels from C80 dbv to C10 dbv. the measured sine wave and triwave responses are 6 db and 8.7 db, respectively, below the square wave responsein agreement with theory. table i. input peak intercept error (relative waveform or rms factor to a dc input) square wave either 1 0.00 db sine wave peak 2 C6.02 db sine wave rms 1.414 ( ? 2 ) C3.01 db triwave peak 2.718 (e) C8.68 db triwave rms 1.569 (e/ ? 3 ) C3.91 db gaussian noise rms 1.887 C5.52 db logarithmic conformance and waveform the waveform also affects the ripple, or periodic deviation from an ideal logarithmic response. the ripple is greatest for dc or square wave inputs because every value of the input voltage maps to a single location on the transfer function and thus traces out the full nonlinearities in the logarithmic response. 2 0 C2 C4 C6 C8 C10 C70 C60 C50 C40 C30 C20 C10 C80 input amplitude in db above 1v, at 10khz square wave input sine wave input triwave input deviation from exact logarithmic transfer function C db figure 22. deviation from exact logarithmic transfer function for two cascaded ad641s, showing effect of waveform on calibration and linearity by contrast, a general time varying signal has a continuum of values within each cycle of its waveform. the averaged output is thereby smoothed because the periodic deviations away from the ideal response, as the waveform sweeps over the transfer function, tend to cancel. this smoothing effect is greatest for a triwave input, as demonstrated in figure 22. the accuracy at low signal inputs is also waveform dependent. the detectors are not perfect absolute value circuits, having a sharp corner near zero; in fact they become parabolic at low levels and behave as if there were a dead zone. consequently, the output tends to be higher than ideal. when there are enough stages in the system, as when two ad641s are connected in cascade, most detectors will be adequately loaded due to the high overall gain, but a single ad641 does not have sufficient gain to maintain high accuracy for low level sine wave or triwave inputs. figure 23 shows the absolute deviation from calibration for the same three waveforms for a single ad641. for inputs between C10 dbv and C40 dbv the vertical displacement of the traces for the various waveforms remains in agreement with the predicted dependence, but significant calibration errors arise at low signal levels. 4 2 0 C2 C4 C6 C8 C10 C70 input amplitude in db above 1v, at 10khz C60 C50 C40 C30 C20 C10 C12 deviation from exact logarithmic transfer function C db square wave input sine wave input triwave input figure 23. deviation from exact logarithmic transfer function for a single ad641, compare low level response with that of figure 22
rev. d ad641 C10C signal magnitude the ad641 is a calibrated device. it is, therefore, important to be clear in specifying the signal magnitude under all waveform conditions. for dc or square wave inputs there is, of course, no ambiguity. bounded periodic signals, such as sinusoids and triwaves, can be specified in terms of their simple amplitude (peak value) or alternatively by their rms value (which is a mea- sure of power when the impedance is specified). it is generally bet- ter to define this type of signal in terms of its amplitude because the ad641 response is a consequence of the input voltage, not power. however, provided that the appropriate value of inter- cept for a specific waveform is observed, rms measures may be used. random waveforms can only be specified in terms of rms value because their peak value may be unbounded, as is the case for gaussian noise. these must be treated on a case-by-case basis. the effective intercept given in table i should be used for gaussian noise inputs. on the other hand, for bounded signals the amplitude can be expressed either in volts or dbv (decibels relative to 1 v). for example, a sine wave or triwave of 1 mv amplitude can also be defined as an input of C60 dbv, one of 100 mv amplitude as C20 dbv, and so on. rms value is usually expressed in dbm (decibels above 1 mw) for a specified impedance level. through- out this data sheet we assume a 50 w environment, the customary impedance level for high speed systems, when referring to signal pow- ers in dbm. bearing in mind the above discussion of the effect of waveform on the intercept calibration of the ad641, it will be apparent that a sine wave at a power of, say, C10 dbm will not produce the same output as a triwave or square wave of the same power. thus, a sine wave at a power level of C10 dbm has an rms value of 70.7 mv or an amplitude of 100 mv (that is, ? 2 times as large, the ratio of amplitude to rms value for a sine wave), while a triwave of the same power has an amplitude which is ? 3 or 1.73 times its rms value, or 122.5 mv. intercept and logarithmic offset if the signals are expressed in dbv, we can write the output current in a simpler form, as: i out = 50 m a (input dbv C x dbv ) equation (4) where input dbv is the input voltage amplitude (not rms) in dbv and x dbv is the appropriate value of the intercept (for a given wave- form) in dbv. this form shows more clearly why the intercept is often referred to as the logarithmic offset. for dc or square wave inputs, v x is 1 mv so the numerical value of x dbv is C60, and equation (4) becomes i out = 50 m a ( input dbv + 60) equation (5) alternatively, for a sinusoidal input measured in dbm (power in db above 1 mw in a 50 w system) the output can be written i out = 50 m a ( input dbm + 44) equation (6) because the intercept for a sine wave expressed in volts rms is at 1.414 mv (from table i) or C44 dbm. operation of a single ad641 figure 24 shows the basic connections for a single device, using 100 w load resistors. output a is a negative going voltage with a slope of C100 mv per decade; output b is positive going with a slope of +100 mv per decade. for applications where absolute calibration of the intercept is essential, the main output (from log out, pin 14) should be used; the log com output can then be grounded. to evaluate the demodulation response, a simple low pass output filter having a time constant of roughly 500 m s (3 db corner of 320 hz) is provided by a 4.7 m f (C20% +80%) ceramic capacitor (erie type rpe117-z5u-475-k50v) placed across the load. a dvm may be used to measure the averaged output in verification tests. the voltage compliance at pins 13 and 14 extends from 0.3 v below ground up to 1 v below +v s . since the current into pin 14 is from C0.2 ma at zero signal to +2.3 ma when fully limited (dc input of >300 mv) the output never drops below C230 mv. on the other hand, the current out of pin 13 ranges from C0.2 ma to +2.3 ma, and if desired, a load resistor of up to 2 k w can be used on this output; the slope would then be 2 v per decade. use of the log com output in this way provides a numerically correct decibel read- ing on a dvm (+100 mv = +1.00 db). board layout is very important. the ad641 has both high gain and wide bandwidth; therefore every signal path must be very carefully considered. a high quality ground plane is essential, but it should not be assumed that it behaves as an equipotential plane. even though the application may only call for modest bandwidth, each of the three differential signal interface pairs (sig in, pins l and 20, sig out, pins 10 and 11, and log, pins 13 and 14) must have their own starred ground points to avoid oscillation at low signal levels (where the gain is highest). output a 10v 11 denotes a short, direct connection to the ground plane. 16 181920 17 9 8 76 10 5 32 14 log out log com sig +out rg2 Cv s sig Cout ad641 rg0 rg1 ckt com atn out sig +in +v s itc bl1 atn in atn com atn com atn lo sig Cin bl2 1kv 1kv nc nc 4.7v C5v nc all unmarked capacitors are 0.1mf ceramic (see text). output b 4.7mf r la 100v 0.1% r lb +5v optional offset balance resistor optional termination resistor signal input 12 13 1415 4.7mf 100v 0.1% figure 24. connections for a single ad641 to verify basic performance
rev. d ad641 C11C unused pins (excluding pins 8, 10 and 11) such as the attenua- tor and applications resistors should be grounded close to the package edge. bl1 (pin 6) and bl2 (pin 9) are internal bias lines a volt or two above the Cv s node; access is provided solely for the addition of decoupling capacitors, which should be con- nected exactly as shown (not all of them connect to the ground). use low impedance ceramic 0.1 m f capacitors (for example, erie rpe113-z5u-105-k50v). ferrite beads may be used instead of supply decoupling resistors in cases where the supply voltage is low. active current-to-voltage conversion the compliance at log out limits the available output volt- age swing. the output of the ad641 may be converted to a larger, buffered output voltage by the addition of an operational amplifier connected as a current-to-voltage (transresistance) stage, as shown in figure 21. using a 2 k w feedback resistor (r2) the 50 m a/db output at log out is converted to a volt- age having a slope of +100 mv/db, that is, 2 v per decade. this output ranges from roughly C0.4 v for zero signal inputs to the ad641, crosses zero at a dc input of precisely +1 mv (or C1 mv) and is +4 v for a dc input of 100 mv. a passive prefilter, formed by r1 and c1, minimizes the high frequency energy conveyed to the op amp. the corner frequency is here shown as 10 mhz. the ad846 is recommended for this appli- cation because of its excellent performance in transresistance modes. its bandwidth of 35 mhz (with the 2 k w feedback resis- tor) will exceed the baseband response of the system in most applications. for lower bandwidth applications other op amps and multipole active filters may be substituted. effect of frequency on calibration the slope and intercept of the ad641 are calibrated during manufacture using a 2 khz square wave input. calibration depends on the gain of each stage being 10 db. when the input frequency is an appreciable fraction of the 350 mhz bandwidth of the amplifier stages, their gain becomes less precise and the logarithmic slope and intercept are no longer as calibrated. figure 10 shows the averaged output current versus input level at 50 mhz, 150 mhz, 190 mhz, 210 mhz, and 250 mhz. figure 11 shows the absolute error in the response at 200 mhz and at temperatures of C55 c, +25 c and +125 c. figure 12 shows the variation in the slope current, and figure 13 shows the variation in the intercept level (sinusoidal input) versus frequency. if absolute calibration is essential, or some other value of slope or intercept is required, there will usually be some point in the users system at which an adjustment may be easily introduced. for example, the 5% slope deficit at 50 mhz (see figure 12) may be restored by a 5% increase in the value of the load resis- tor in the passive loading scheme shown in figure 24, or by inserting a trim potentiometer of 100 w in series with the feed- back resistor in the scheme shown in figure 21. the intercept can be adjusted by adding or subtracting a small current to the output. since the slope current is 1 ma/decade, a 50 m a incre- ment will move the intercept by 1 db. note that any error in this current will invalidate the calibration of the ad641. for example, if one of the 5 v supplies were used with a resistor to generate the current to reposition the intercept by 20 db, a 10% variation in this supply will cause a 2 db error in the absolute calibration. of course, slope calibration is unaffected. source resistance and input offset the bias currents at the signal inputs (pins 1 and 20) are typi- cally 7 m a. these flow in the source resistances and generate input offset voltages which may limit the dynamic range because the ad641 is direct coupled and an offset is indistinguishable from a signal. it is good practice to keep the source resistances as low as possible and to equalize the resistance seen at each input. for example, if the source resistance to pin 20 is 100 w , a compensating resistor of 100 w should be placed in series with pin 1. the residual offset is then due to the bias current offset, which is typically under 1 m a, causing an extra offset uncertainty of 100 m v in this example. for a single ad641 this will rarely be troublesome, but in some applications it may need to be nulled out, along with the internal voltage offset component. this may be achieved by adding an adjustable voltage of up to 250 m v at the unused input. (pins 1 and 20 may be interchanged with no change in function.) in most applications there will be no need to use any offset adjustment. however, a general offset trimming circuit is shown in figure 25. r s is the source resistance of the signal. note: 50 w rf sources may include a blocking capacitor and have no dc path to ground, or may be transformer coupled and have a near zero resis- tance to ground. determine whether the source resistance is zero, 25 w or 50 w (with the generator terminated in 50 w ) to find the cor rect value of bias compensating resistor, r b , which should optimally be equal to r s , unless r s = 0, in which case use r b = 5 w . the value of r os should be set to 20,000 r b to provide a 250 m v trim range. to null the offset, set the source voltage to zero and use a dvm to observe the logarithmic out- put voltage. recall that the log out current of the ad641 exhibits an absolute value response to the input voltage, so the offset potentiometer is adjusted to the point where the logarithmic output turns around (reaches a local maximum or minimum). at high frequencies it may be desirable to insert a coupling capacitor and use a choke between pin 20 and ground, when pin 1 should be taken directly to ground. alternatively, trans- former coupling may be used. in these cases, there is no added offset due to bias currents. when using two dc-coupled ad641s (overall gain 100,000), it is impractical to maintain a sufficiently low offset voltage using a manual nulling scheme. the section cascaded operation explains how the offset can be automatically nulled to submicrovolt levels by the use of a nega- tive feedback network. C5v (source resistance of terminated generator) r b 2 19 1 20 r os r s +5v 20kv ad641 figure 25. optional input offset voltage nulling circuit; see text for component values
rev. d ad641 C12C using higher supply voltages the ad641 is calibrated using 5 v supplies. scaling is very insensitive to the supply voltages and higher supply voltages will not directly cause significant errors. however, the ad641 power dissipation must be kept below 500 mw in the interest of reli- ability and long term stability. when using well regulated supply voltages above 6 v, the decoupling resistors shown in the application schematics can be increased to maintain 5 v at the ic. the resistor values are calculated using the specified maxi- mum of 15 ma current into the +v s terminal (pin 12) and a maximum of 60 ma into the Cv s terminal (pin 7). for example, when us ing 9 v supplies, a resistor of (9 v C 5 v)/15 ma, about 261 w , should be included in the +v s lead to each ad641 and (9 v C 5 v)/60 ma, about 64.9 w in each Cv s lead. of course, asymmetric supplies may be dealt with in a similar way. using the attenuator in applications where the signal amplitude is sufficient, the on- chip attenuator should be used because it provides a tempera- ture independent dynamic range (compare figures 18 and 19). figure 26 shows this attenuator in more detail. r1 is a thin-film 4 17 3 18 2 19 1 20 5 atn com 16 sig Cin sig +in atn com atn lo atn in r3 r4 r1 r2 atn out first amplifier input figure 26. details of the input attenuator resistor of nominally 270 w and low temperature coefficient (tc). it is trimmed to calibrate the intercept to 10 mv dc (or C24 dbm for sinusoidal inputs), that is, to an attenuation of nominally 20 dbs at +27 c. r2 has a nominal value of 30 w and has a high positive tc, such that the overall attenuation factor is 0.33%/ c at +27 c. this results in a transmission factor that is proportional to absolute temperature, or ptat. (see intercept stabilization for further explanation.) to improve the accuracy of the attenuator, the atn com nodes are bonded to both pin 3 and pin 4. these should be connected directly to the slgnal low of the source (for example, to the grounded side of the signal connector, as shown in figure 32) not to an arbitrary point on the ground plane. r4 is identical to r2, and in shunt with r3 (270 w thin film) forms a 27 w resistor with the same tc as the output resistance of the attenuator. by connecting pin 1 to atn low (pin 2) this resistance minimizes the offset caused by bias currents. the offset nulling scheme shown in figure 25 may still be used, with the external resistor r b omitted and r os = 500 k w . offset stabil- ity is improved because the compensating voltage introduced at pin 20 is now ptat. drifts of under 1 m v/ c (referred to pins 1 and 20) can be maintained using the attenuator. it may occasionally be desirable to attenuate the signal even further. for example, the source may have a full-scale value of 10 v, and since the basic range of the ad641 extends only to 200 mv dc, an attenuation factor of 50 might be chosen. this may be achieved either by using an independent external attenuator or more simply by adding a resistor in series with atn in (pin 5). in the latter case the resistor must be trimmed to calibrate the intercept, since the input resistance at pin 5 is not guaranteed. a fixed resistor of 1 k w in series with a 500 w variable resistor calibrate to an intercept of 50 mv (or C26 dbv) for dc or square wave inputs and provide a 10 v input range. the intercept stability will be degraded to about 0.003 db/ c. nc denotes a connection to the ground plane; observe common connections where shown. all unmarked capacitors are 0.1mf ceramic. for values of numbered components see text 10v nc nc r1 r2 signal input c1 c2 4.7v 4.7v C5v +5v 1ma/decade output C50mv/decade c3 r l = 50v 9 87 6 10 5 32 14 12 1314 15 11 16 181920 17 log out log com sig +out rg2 Cv s sig Cout rg0 rg1 ckt com atn out sig +in +v s itc bl1 atn in atn com atn com atn lo sig Cin bl2 1kv 1kv u1 ad641 9 87 6 10 5 32 14 12 1314 15 11 16 181920 17 log out log com sig +out rg2 Cv s sig Cout rg0 rg1 ckt com atn out sig +in +v s itc bl1 atn in atn com atn com atn lo sig Cin bl2 1kv 1kv u2 ad641 10v 10v 10v figure 27. basic connections for cascaded ad641s
rev. d ad641 C13C operation of cascaded ad641s frequently, the dynamic range of the input will be 50 db or more. two ad641s can be cascaded, as shown in figure 27. the balanced signal output from u1 becomes the input to u2. resistors are included in series with each log out pin and capacitors c1 and c2 are placed directly between pins 13 and 14 to provide a local path for the rf current at these output pairs. c1 through c3 are chosen to provide the required low pass corner in conjunction with the load r l . board layout and grounding disciplines are critically important at the high gain (x100,000) and bandwidth (~ 150 mhz) of this system. the intercept voltage is calculated as follows. first, note that if its log out is disconnected, u1 simply inserts 50 db of gain ahead of u2. this would lower the intercept by 50 db, to C110 dbv for square wave calibration. with the log out of u1 added in, there is a finite zero signal current which slightly shifts the intercept. with the intercept temperature compensa- tion on u1 disabled this zero signal output is C270 m a equiva- lent to a 5.4 db upward shift in the intercept, since the slope is 50 m a/db. thus, the intercept is at C104.6 dbv (C88 dbm for 50 w sine calibration). itc may be disabled by grounding pin 8 of either u1 or u2. cascaded ad641s can be used in dc applications, but input offset voltage will limit the dynamic range. the dc intercept is 6 m v. the offset should not be confused with the intercept, which is found by extrapolating the transfer function from its central log linear region. this can be understood by referring to equation (1) and noting that an input offset is simply additive to the value of v in in the numerator of the logarithmic argument; it does not affect the denominator (or intercept) v x . in dc coupled applica- tions of wide dynamic range, special precautions must be taken to null the input offset and minimize drift due to input bias offset. it is recommended that the input attenuator be used, providing a practical input range of C74 dbv ( 200 m v dc) to +6 dbv ( 2 v dc) when nulled using the adjustment circuit shown in figure 25. 1920 21 u2 12 11 910 u1 1920 21 u2 12 11 910 u1 (a) ( b ) figure 28. two methods for ac coupling ad641s eliminating the effect of first stage offset usually, the input signal will be sinusoidal and u1 and u2 can be ac coupled. figure 28a shows a low resistance choke at the input of u2 which shorts the dc output of u1 while preserving the hf response. coupling capacitors may be inserted (figure 28b) in which case two chokes are used to provide bias paths for u2. these chokes must exhibit high impedance over the operat- ing frequency range. alternatively, the input offset can be nulled by a negative feed- back network from the sig out nodes of u2 to the sig in nodes of u1, as shown in figure 29. the low pass response of the feedback path transforms to a closed-loop high pass response. the high gain ( 100,000) of the signal path results in a com- mensurate reduction in the effective time constant of this net- work. for example, to achieve a high pass corner of 100 khz, the low pass corner must be at 1 hz. in fact, it is somewhat more complicated than this. when the ac input sufficiently exceeds that of the offset, the feedback be- comes ineffective and the response becomes essentially dc coupled. even for quite modest inputs the last stage will be limiting and the output (pins 10 and 11) of u2 will be a square wave of about 180 mv amplitude, dwelling approximately equal times at its two limit values, and thus having a net average value near zero. only when the input is very small does the high pass behavior of this nulling loop become apparent. consequently, the low pass time constant can usually be reduced considerably without serious performance degradation. the resistor values are chosen such that the dc feedback is adequate to null the worst case input offset, say, 500 m v. there must be some resistance at pins 1 and 20 across which the offset compensation voltage is developed. the values shown in the figure assume that we wish to terminate a 50 w source at pin 20. the 50 w resistor at pin 1 is essential, both to minimize offsets due to bias current mismatch and because the outputs at pins 10 and 11 can only swing negatively (from ground to C180 mv) whereas we need to cater for input offsets of either polarity. for a sine input of 1 m v amplitude (C120 dbv) and in the ab- sence of offset, the differential voltage at pins 10 and 11 of u2 would be almost sinusoidal but 100,000 times larger, or 100 mv. the last limiter in u2 would be entering saturation. a 1 m v input offset added to this signal would put the last limiter well into saturation, and its output would then have a different aver- age value, which is extracted by the low pass network and deliv- ered back to the input. for larger signals, the output approaches a square wave for zero input offset and becomes rectangular when offset is present. the duty cycle modulation of this output now produces the nonzero average value. assume a maximum re- quired differential output of 100 mv (after averaging in c1 and c2) as shown in figure 29. r3 through r6 can now be chosen to provide 500 m v of correction range, and with these values the input offset is reduced by a factor of 500. using 4.7 m f capacitors, the time constant of the network is about 1.2 ms, and its corner frequency is at 13.5 hz. the closed loop high pass corner (for small signals) is, therefore, at 1.35 mhz. 20 110 11 u1 a ve = C140mv input 20 110 11 u2 r1 50v r2 50v c1 c2 a ve = C140mv r3 4.99kv r5 4.99kv C200mv C700mv 4ma 14ma r4 4.99kv r6 4.99kv figure 29. feedback offset correction network
rev. d ad641 C14C practical applications we show here two applications, using ad641s to achieve a wide dynamic range. as already mentioned, the use of a differential signal path and differential logarithmic outputs diminishes the risk of instability due to poor grounding. nevertheless, it must be remembered that at high frequencies even very small lengths of wire, including the leads to capacitors, have significant im- pedance. the ground plane itself can also generate small but troublesome voltages due to circulating currents in a poor lay- out. a printed circuit evaluation board is available from analog devices (part number ad641-eb) to facilitate the prototyping of an application using one or two ad641s, plus various exter- nal components. at very low signal levels various effects can cause significant deviation from the ideal response, apart from the inherent non- linearities of the transfer function already discussed. note that any spurious signal presented to the ad641s is demodulated and added to the output. thus, in the absence of thorough shielding, emissions from any radio transmitters or rfi from equipment operating in the locality will cause the output to appear too high. the only cure for this type of error is the use of very care- ful grounding and shielding techniques. rssi applications the ad641 can be used to perform an rssi (received signal strength indicator) function. this is a commonly used function in radio receivers, but can be used in other instrumentation such as photomultiplier tubes. the signal strength indicator on fm radios is one example of an rssi application. it is this signal that is monitored to determine where to stop during seek or scan operations. the ad641 is used to measure the strength of the incoming rf signal and outputs a current that is proportional to the loga- rithm of its ac amplitude. in this manner signal amplitudes with a wide dynamic range and wide bandwidth can be measured. 250 mhz rssi converter with 44 db dynamic range figure 30 shows the schematic for an rssi circuit that uses a single ad641. the dynamic range for this circuit using a single ad641 is 44 db. the ad641 amplifies and full wave rectifies (detects) the input and outputs a current. the ad846 is used to convert the current to a ground referenced voltage. with a 1 k w feedback resistor, the output varies by 1 v/decade or 50 mv/db. 6 7 4 3 C6v 4.7v u3 ad846 rssi output +50mv/db (lo) +6v 2 c1 47pf 4.7v nc denotes a connection to the ground plane; observe common connections where shown. all unmarked capacitors are 0.1mf ceramic. for values of numbered components see text r1 r2 signal input 18v 68v 1.0kv 9 87 6 10 5 32 14 12 1314 15 11 16 181920 17 log out log com sig +out rg2 Cv s sig Cout rg0 rg1 ckt com atn out sig +in +v s itc bl1 atn in atn com atn com atn lo sig Cin bl2 1kv 1kv u1 ad641 C6v +6v r3 100v figure 30. rssi using single ad641
rev. d ad641 C15C frequency C mhz 3 2.5 C0.5 1 1000 10 100 2 1.5 1 0.5 0 volts C log out into 1k 0dbm C20dbm C35dbm C50dbm figure 31. single ad641 rssi vs. frequency figure 31 shows a plot of rssi vs. frequency for various input signal amplitudes. it can be seen that at higher frequencies the output drops off as explained in the section effect of fre- quency on calibration. if the rssi circuit is to be operated at a known frequency with limited bandwidth, the compensation techniques described in that section can be used to enhance accuracy. 250 mhz rssi converter with 58 db dynamic range for a larger dynamic range two ad641s can be cascaded, as shown in figure 32. the low end usefulness of the circuit will be set by the noise floor of the overall environment that the circuit sees. this includes all sources of both radiated and conducted noise. proper layout to avoid conducted noise and good shield- ing to minimize radiated noise are essential for good low signal operation. frequency C mhz 4.5 3.5 0 1 1000 10 100 2 2.5 1 1.5 0.5 volts C log out into 1k 0dbm C20dbm C50dbm C80dbm 4 3 figure 33. cascaded ad641s rssi vs. frequency filtering between the devices and input offset nulling techniques described elsewhere are also useful for extending the dynamic range of two cascaded devices. figure 33 shows a plot of this circuit vs. frequency for various input amplitudes. the drop off at high frequency can be seen to be greater than for the single device case due to the compound- ing effects of the bandwidth limiting of the extra stages. 6 7 4 3 u3 ad846 2 C6v 4.7v log output +50mv/db (lo) +6v 4.7v l1 (see text) (see text) r5 1.13kv c2 47pf c1 47pf +6v 68v r4 100v C6v 18v nc denotes a connection to the ground plane; observe common connections where shown. all unmarked capacitors are 0.1mf ceramic. for values of numbered components see text r3 100v nc nc r1 r2 signal input 9 87 6 10 5 32 14 12 1314 15 11 16 181920 17 log out log com sig +out rg2 Cv s sig Cout rg0 rg1 ckt com atn out sig +in +v s itc bl1 atn in atn com atn com atn lo sig Cin bl2 1kv 1kv u1 ad641 9 87 6 10 5 32 14 12 1314 15 11 16 181920 17 log out log com sig +out rg2 Cv s sig Cout rg0 rg1 ckt com atn out sig +in +v s itc bl1 atn in atn com atn com atn lo sig Cin bl2 1kv 1kv u2 ad641 68v 18v figure 32. complete 58 db dynamic range converter for 250 mhz operation
ad641 rev. d | page 16 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 070706-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 20 1 10 11 0.100 (2.54) bsc 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) fig ure 33. 20-lead plastic dual in-line package [pdip] narrow body (n-20) dimensions shown in inches and (millimeters) compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier fig ure 34. 20-lead plastic leaded chip carrier [plcc] (p-20) dimensions shown in inches and (millimeters)
ad641 rev. d | page 17 20 1 10 11 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.060 (26.92) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. figure 3 5. 20-lead ceramic dual in-line package [cerdip] (q-20) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option ?40c to +85c 20-le ad pdip n-20 ?40c to +85c 20-le ad plcc p-20 AD641ANZ ad641apz 5962-955980 2mra ?55c to +125c 20-lead cerdip q-20 1 z = rohs compliant part. ?1999C2016 anal og devices, inc. all rights reserv ed. tra demarks and registered trademarks are the property of their respective owners. c2014c-0-6/16(d)

▲Up To Search▲

Price & Availability of AD641ANZ

	To Download AD641ANZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .